Tampa, Florida – June 29 to July 2, 2026
ALD/ALE 2026 is behind us. Chipmetrics contributed two presentations this year, an oral talk on high surface area micro-loading effect and a poster on platinum ALD with Aalto University. We also had the pleasure of seeing PillarHall user cases appear on other slides and posters. Here is our wrap-up.
Our talk: nearby surface area changes your conformality
Novel method to quantify high surface area micro-loading effects on film conformality
Jussi Kinnunen, Kalle Eskelinen, Stefan Polzin, Gao Feng, Mikko Utriainen (Chipmetrics)
This started as an in-house annoyance rather than a research plan. We had optimized an ALD process using PillarHall chips during the development phase, then ran production on chips carrying high surface area deep hole arrays, with a PillarHall chip riding along as a control. The control told us plainly that something had changed between development and production. Same recipe, same chamber, the only real difference was a load now carrying a very large amount of extra surface area.
That suggested a simple hypothesis: a high surface area structure acts as a local precursor sink and depresses the partial pressure around it. If so, the effect has to be a function of distance. So we measured conformality (50% penetration depth) on different PillarHall test structures at increased distances from a high surface area structure.
The result. ALD conformality falls sharply near the high surface area structure and recovers gradually with distance, following a clear linear trend. Closest in, roughly a quarter of the penetration was lost compared with a reference chip that had no high surface loading nearby, and even 13 millimeters away the effect had not fully disappeared. This is a gradient across a meaningful fraction of a wafer, not a local artefact.
Feeding the measured profiles into a published diffusion–reaction model enables us to turn the observation into a number: local precursor partial pressure near the high surface loading structure is around 45% lower than at the reference position.
Why it matters. If you run conformality as an SPC parameter, wafer-level control is not the whole story. Local high surface area on the same wafer shifts the answer, and two control chips in different spots can legitimately tell the difference. Pairing LHAR measurement with modelling turns that from a puzzle into a quantity you can track.
Our poster: Pt conformality and conductivity on the same chip
Studies of Pt ALD film conformality and conductivity with PillarHall test structures
Chipmetrics Oy and GmbH, with Aalto University
Noble metal ALD is a hard metrology problem: expensive precursors, narrow process windows, and conventional tools that struggle once the film is metallic. Together with Aalto University, we showed what we believe is the first combined conformality and electrical characterization of Pt ALD on a single test structure.
The enabler is a released and pillar-stabilized membrane. After the ALD film deposition, the membrane is lifted off with tape, leaving a prepatterned anchored area with narrow line and probe pads at each end, an electrical test structure that was predesigned by the membrane shape. No photolithography, no etching, and it works regardless of whether the film is a material you could etch or not in the first place.
Optical measurement could trace film thickness along the narrow line up to about 30 nm of Pt, above which the response saturates, a useful reminder of where optical metrology runs out for metals. Four-probe measurements on the same chips showed clean metallic behavior across a wide temperature range, with the effect of the dielectric precoating clearly visible. Next up: AFM-based conductivity mapping and correlated SEM/EDS.
Lateral High Aspect Ratio (LHAR) data beyond our own slides
Lateral high aspect ratio test structures were also featured in several presentations by other groups during the week.
Hiroshi Nishizato and colleagues (Kumamoto University, with HORIBA STEC and the University of Yamanashi) presented a method for characterizing ALD conformality that pairs imaging ellipsometry with a lateral high aspect ratio test structure. By building imaging capability into a custom ellipsometer, they read the penetration depth of the film from an image of the channel rather than measuring point by point. Using Al₂O₃ from TMA and water, they reported that growth per cycle on planar silicon was unaffected by precursor dose while penetration depth inside the lateral structure continued to increase with higher dose, a planar wafer indicating saturation while the reach into a real feature was still changing. Their stated next step is to move the measurement inside the ALD chamber for real-time monitoring.
Soham Shirodkar and colleagues (University of Texas at Dallas, with RASIRC) presented a poster on how the choice of oxidant affects conformal HZO deposition in high aspect ratio structures. Work carried out on the PillarHall chips they won as the prize in our conformality research competition at ALD 2024.
The question they set out to answer is a practical one for DRAM capacitor scaling. Hf-based high-k oxides are typically deposited with ozone, but ozone’s strong oxidizing power can attack the metal electrode, and recombination costs oxidant before it reaches the bottom of a deep feature. The group evaluated hydrogen peroxide as an alternative. Using cross-sectional SEM and EDS line profiles to quantify how far the film penetrated, they compared a short and a long peroxide dose against an ozone process and reported penetration corresponding to aspect ratios of roughly 50:1, 800:1 and 180:1 respectively. Their conclusion was that within the process window, filling depends more strongly on the hafnium precursor dose than on which oxidant was used, and that at extreme aspect ratios, precursor transport rather than oxidant chemistry is likely to be the limiting factor. They also compared vertical and horizontal geometries and found their experimental results in good agreement with kinetic HAR filling models.
The wider program
High aspect ratio came up constantly, and almost always in the context of what comes next: logic, 3D NAND, DRAM and above all 3D DRAM, where ALD is not one option among several but a requirement. The architectures and the material choices are still openly in play, which makes the ability to characterize a process independently of any particular device structure more useful, not less.
Two themes stood out for how people intend to measure all this. The first is that across-wafer measurement is becoming important for essentially every feature and parameter. A single number from a single spot is no longer a satisfying answer. That matches what we found in our own micro-loading work, where the answer depended on where the chip sat. The second is that studying an ALD step in isolation is no longer enough. An integration view is taking over, which means adding the further layers and structures needed to get at electrical performance rather than stopping at thickness and composition. That is precisely the direction our Pt conformality work with Aalto is heading.
