NAND flash memory is a pivotal non-volatile storage technology utilized across various electronic devices. It has transitioned from 2D planar NAND to 3D NAND to accommodate the escalating demands for enhanced storage density and performance. This evolution towards vertical layering continues unabated [1].
Critical Role of ALD in 3D NAND Fabrication: Atomic Layer Deposition (ALD) is essential in the fabrication of 3D NAND, due to its ability to deposit ultra-thin, highly conformal films with precise thickness control. However, the ongoing scaling up of 3D NAND presents several challenges impacting performance, yield, and cost.
Major Challenges:
1. Film Conformality in High Aspect Ratio Structures:
As 3D NAND architectures evolve, they feature increasingly higher aspect ratios due to more layers being stacked vertically (e.g., 128, 192, or 256 layers). ALD must ensure film uniformity inside deep, narrow trenches and holes—vital for channels and gates—which becomes increasingly challenging with scale. Poor conformality can lead to uneven electrical properties and, ultimately, device failure, particularly critical in gate dielectric or barrier layers.
2. Uniformity of Conformality vs. Film Thickness Across the Wafer:
The precise, self-limiting nature of ALD can be compromised by non-uniform precursor distribution, temperature fluctuations, and varying reaction kinetics over large substrate areas. This results in film conformality variations across different locations on a 300 mm wafer, posing significant risks to device consistency and reliability.
Addressing these challenges requires innovative solutions in process control, equipment design, and material handling to ensure the robust performance of ALD in 3D NAND production
The PillarHall test chips are specialized test structures designed to help in evaluating the conformality of thin film deposition techniques such as Atomic Layer Deposition (ALD) in High Aspect Ratio (HAR) structures. They provide a reliable and efficient way to characterize and quantify how well thin films cover the surfaces of deep, narrow trenches or cavities in 3D structures, which is a critical requirement in applications like 3D NAND memory. With the help of Pocket wafers, PillarHall test chips can be used to evaluate the conformality across the wafer which is otherwise very difficult to measure.
The PillarHall test chip contains lateral high aspect ratio (LHAR) structures which covers aspect ratio as high as 50000:1. The constant gap height (which mimics the vertical trench width) ensures very accurate and reliable measurement results of the film penetration depth into the HAR structures. These results can be compared with real 3D NAND device structures and correlating models can be established in a HAR calculator for easy film conformality estimations.
The evolution of 3D NAND technology has significantly enhanced storage density and performance. As the industry progresses, the next generation of 3D NAND will necessitate further innovations in materials and deposition techniques to meet increasing demands. Key challenges such as achieving conformality in high aspect ratios, enhancing throughput, ensuring uniformity, and reducing costs are critical for supporting the aggressive scaling needs of the memory industry.
Advanced ALD techniques, new precursor developments, and process optimizations will be critical in overcoming these challenges.
Chipmetrics’ high aspect ratio test chips, particularly the PillarHall test chips, are instrumental in enabling industry players to evaluate thin film conformality during the 3D NAND fabrication process in a more accurate, fast, and cost-effective manner. These test chips allow for the effective assessment and optimization of ALD processes in high aspect ratio structures, eliminating the need for complex and costly real-world test setups. As a result, PillarHall test chips are invaluable tools for advancing thin film deposition technologies in semiconductor manufacturing, significantly contributing to the development of next-generation 3D NAND.
[1] Dielectric Engineering to Suppress Cell-to-Cell Programming Voltage Interference in 3D NAND Flash Memory, https://www.mdpi.com/2072-666X/12/11/1297
[2] KIOXIA’s BiCS FLASH™ memory cell, https://www.kioxia.com/en-jp/rd/technology/bics-flash.html
Chipmetrics is a leader in the semiconductor 3D metrology, offering cutting-edge solutions for process control through its innovative test chips and wafers.
Our core technologies provide a new perspective in measuring 3D thin films within high aspect ratio device architectures, enabling precise and rapid assessments crucial for development and manufacturing.
We specialize in assisting our clients to develop new materials, optimize deposition processes, and enhance overall yields, significantly accelerating their time to market.
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