Spotting a “Second Growth Front” in ALD Trenches
Atomic Layer Deposition (ALD) is prized for coating deep, high-aspect-ratio (HAR) features. Using Chipmetrics’ PillarHall® lateral HAR test structures, we have now identified an unexpected second growth front that starts at the closed end of the trench and advances toward the entrance, meeting the primary front in the middle. How we saw it Imaging spectroscopic […]
Unlocking Bottleneck Effects in 3D Semiconductor Structures with PillarHall Lateral High Aspect Ratio(LHAR) Test Chips
The Challenge: Conformality in Complex Geometries Atomic Layer Deposition (ALD) is the go-to technique for achieving ultra-thin, conformal films in the deep, narrow features found in advanced semiconductors, batteries, and capacitors. However, as device designs push into ever-more complex 3D geometries, a hidden challenge emerges: bottlenecks in High Aspect Ratio (HAR) structures can disrupt film […]
Chipmetrics Expands Product Line with Advanced ALD Test Chips and Wafer Solutions
Finnish 3D thin film semiconductor metrology specialist expands its metrology portfolio with advanced test chips and wafer solutions that accelerate prototyping and precision analysis for next-generation semiconductor processes. Joensuu, Finland – August 14th, 2025 – Chipmetrics, a leader in innovative metrology solutions for atomic layer deposition (ALD) and advanced semiconductor processes, announces the expansion of […]
Optimizing ALD in 3D Structures: How PillarHall® Chips Make It Easier
Atomic Layer Deposition (ALD) has become the go-to solution for coating complex 3D structures in semiconductor manufacturing and advanced packaging. But achieving uniform, conformal coatings in high-aspect-ratio (HAR) features remains a major challenge, especially when traditional measurement tools fall short. That’s where the PillarHall chip comes in. At Chipmetrics, we’ve developed the PillarHall chip specifically […]
Spatial Atomic Layer Deposition (ALD): Unveiling New Frontiers in Material Processing with Mike van de Poll
Mike van de Poll, a researcher at Eindhoven University of Technology, has dedicated his scientific endeavors to exploring the intricacies of spatial Atomic Layer Deposition (ALD). Supervised by renowned experts in the field, Erwin Kessels and Bart Macco, Mike’s research dives deep into understanding fundamental aspects of spatial ALD, leveraging the advanced capabilities of Chipmetrics’ […]
Our Picks Ahead of ALD/ALE 2025
Anticipating Atomic Layer Innovation in South Korea As the semiconductor industry surges toward ever-more complex device architectures, ALD 2025 stands out as a premier venue for discovering the innovations that will define next-generation atomic-scale processing. From addressing high aspect ratio (HAR) challenges to developing new materials and precision etching techniques, the conference program is packed […]
Enabling Next-Generation Silicon Capacitors with ALD and PillarHall
As electronic systems continue to scale in speed, complexity, and miniaturization, the demands placed on power delivery and signal integrity have never been greater. Silicon capacitors, key components for decoupling and noise suppression in high-performance circuits, must now meet extreme requirements for low impedance, high capacitance density, and minimal parasitics – all within shrinking footprints. […]
PillarHall®: Speeding Up ALD Process Development for CIS Manufacturing
Atomic Layer Deposition (ALD) plays a crucial role in CMOS Image Sensor (CIS) manufacturing, especially when dealing with the demanding challenges presented by high aspect ratio (HAR) structures. Engineers involved in CIS production frequently encounter hurdles such as inconsistent thin-film coverage, poor step conformality, and prolonged optimization cycles – all factors impacting sensor reliability, image […]
Driving Innovation in Semiconductors with Area Selective Deposition (ASD)
As semiconductor devices continue to shrink and performance demands rise, advanced techniques become indispensable for manufacturers seeking to stay ahead of the technological curve. One such technique is area selective deposition (ASD). ASD enables the precise deposition of materials on specific regions of a wafer while preventing deposition on unwanted areas. This approach holds significant […]
The PillarHall® LHAR5 and Advanced Semiconductor Process Control
In today’s fast-paced semiconductor industry, the margin for error continues to shrink with each new device node. At the same time, competition is fiercer than ever, driving the need for faster tool qualification, higher yield, and more sustainable production processes. That’s why we’re excited to introduce the fifth generation PillarHall test chip, LHAR5 – a […]
