Spatial Atomic Layer Deposition (ALD): Unveiling New Frontiers in Material Processing with Mike van de Poll
Mike van de Poll, a researcher at Eindhoven University of Technology, has dedicated his scientific endeavors to exploring the intricacies of spatial Atomic Layer Deposition (ALD). Supervised by renowned experts in the field, Erwin Kessels and Bart Macco, Mike’s research dives deep into understanding fundamental aspects of spatial ALD, leveraging the advanced capabilities of Chipmetrics’ […]
Our Picks Ahead of ALD/ALE 2025
Anticipating Atomic Layer Innovation in South Korea As the semiconductor industry surges toward ever-more complex device architectures, ALD 2025 stands out as a premier venue for discovering the innovations that will define next-generation atomic-scale processing. From addressing high aspect ratio (HAR) challenges to developing new materials and precision etching techniques, the conference program is packed […]
Enabling Next-Generation Silicon Capacitors with ALD and PillarHall
As electronic systems continue to scale in speed, complexity, and miniaturization, the demands placed on power delivery and signal integrity have never been greater. Silicon capacitors, key components for decoupling and noise suppression in high-performance circuits, must now meet extreme requirements for low impedance, high capacitance density, and minimal parasitics – all within shrinking footprints. […]
PillarHall®: Speeding Up ALD Process Development for CIS Manufacturing
Atomic Layer Deposition (ALD) plays a crucial role in CMOS Image Sensor (CIS) manufacturing, especially when dealing with the demanding challenges presented by high aspect ratio (HAR) structures. Engineers involved in CIS production frequently encounter hurdles such as inconsistent thin-film coverage, poor step conformality, and prolonged optimization cycles – all factors impacting sensor reliability, image […]
Driving Innovation in Semiconductors with Area Selective Deposition (ASD)
As semiconductor devices continue to shrink and performance demands rise, advanced techniques become indispensable for manufacturers seeking to stay ahead of the technological curve. One such technique is area selective deposition (ASD). ASD enables the precise deposition of materials on specific regions of a wafer while preventing deposition on unwanted areas. This approach holds significant […]
Challenges of Transferring Deposition Processes to Industry Partners in the Semiconductor Industry
The ongoing struggle to uphold Moore’s law leads to increasing scaling demands for semiconductor device structures. In order to facilitate these needs the introduction of 3D structures has been accelerated by the industry. This is especially evident in 3D NAND memory structures, Though Silicon Vias (TSVs) and new transistor architectures like nanosheet designs. All of […]
Streamline Semiconductor Tool Qualification with PillarHall Test Chips
Staying competitive hinges on getting new tools up and running as quickly and efficiently as possible, be it brand new tools or after maintenance. Yet, the qualification process for deposition equipment can be a major bottleneck – one that often involves lengthy cycles, costly materials, and complex data analysis. Our PillarHall series of test chips […]
The PillarHall® LHAR5 and Advanced Semiconductor Process Control
In today’s fast-paced semiconductor industry, the margin for error continues to shrink with each new device node. At the same time, competition is fiercer than ever, driving the need for faster tool qualification, higher yield, and more sustainable production processes. That’s why we’re excited to introduce the fifth generation PillarHall test chip, LHAR5 – a […]
PillarHall LHAR Structures at the Forefront of ALD/ALE2024 Conference
The ALD/ALE2024 conference is showcasing the PillarHall Lateral High Aspect Ratio (LHAR) test structure in numerous pivotal presentations this year. This trend underscores the importance and versatility of PillarHall structure in pushing the boundaries of conformality research and ALD technology. Key Presentations Featuring PillarHall Structures Unveiling ALD Reaction MechanismsDr. Jussi Kinnunen will discuss the influence […]
Chipmetrics Launches New Test Chips for Advanced Atomic Layer Processes
Finnish 3D thin film semiconductor metrology specialist launches new PillarHall LHAR5 test chip with 100 nanometer gap height, complements its metrology solution with new ASD-1 chip for Area Selective Deposition. Joensuu, Finland – July 15th, 2024 – Chipmetrics Oy, an innovative metrology solutions provider to the semiconductor industry, announces the launch of two new test chips, the […]
