The ongoing struggle to uphold Moore’s law leads to increasing scaling demands for semiconductor device structures. In order to facilitate these needs the introduction of 3D structures has been accelerated by the industry. This is especially evident in 3D NAND memory structures, Though Silicon Vias (TSVs) and new transistor architectures like nanosheet designs. All of these structures require high aspect ratio deposition processes able to uniformly coat structures with aspect ratios exceeding 100:1.
To achieve this, Atomic Layer Deposition (ALD) processes are required. Like every challenge this also represents an opportunity for researchers to introduce novel approaches to the semiconductor industry. In order to be successful, a number of factors need to be considered:
Development will likely occur using lab equipment. While offering flexibility it usually is not representative of high-throughput manufacturing tools. Differences in chamber design may lead to unexpected results when transferred. Furthermore, if development takes place on smaller wafers there may be across-wafer deviations observable on 300-millimeter substrates. Thus, the scalability to an industrial context must be considered early in the process.
Semiconductor manufacturing is an expensive endeavor. Besides the high operating costs of a cleanroom, it needs to be considered that each manufacturing tool represents a significant investment. To recuperate these costs efficient operation of each tool becomes mandatory. This requires processes with high throughput and long tool uptimes between service intervals. Otherwise good ALD process may not be implemented due to low deposition rates or higher maintenance costs.
Yield is a key parameter in every semiconductor fab in the world. Achieving high yields requires meticulous defect control. Any foreign particle will negatively effect yield and thus must be avoided. The potential for particle generation during ALD deposition needs to be considered early in the development process. Research organizations usually do not have access to leading edge cleanroom environments and furthermore lack defect detection equipment. This makes partnering with a leading-edge semiconductor player essential for successful process transfer.
In recent years the trend of globalization has started to reverse, especially in the semiconductor space. This increasingly causes strain on the supply chain. It must be considered that process materials like precursors may not be available in certain regions of the world. Furthermore, differences in EHS regulation between regions may forbid the use of certain materials in some areas. Thus, it is essential to only consider materials which fulfill these requirements and can be sourced in the region where the process is intended to be used.
Once all this is taken into account, the process needs to be evaluated on relevant test structures. Since most research facilities do not have access to Silicon structures with features sizes below 100 nanometer (nm) or aspect ratios above 100:1, obtaining such structures becomes a challenge. To add further challenge, semiconductor manufacturers only reluctantly share test structures due to IP concerns, while very advanced sample preparation and analysis methods are required to characterize the results of high aspect ratio depositions.
The Chipmetrics PillarHall family of metrology chips offers solution to these problems. They feature dedicated structures with aspect ratios up to 10,000:1, which can be analyzed without the need for cross-sections. This innovation speeds up the development of high aspect ratio film depositions at lower cost than by use of traditional methods. The idea is that results achieved with the PillarHall structures help prepare companies and researchers qualify their processes for use by potential partners in the semiconductor industry.
