TSV R&D: Everyone’s Problem in Advanced Packaging
Vertical connectivity is a key element of Advanced Packaging: The implementation of Silicon Interposers and chip stacking allows shorter and more dense electrical connections which reduce signal delay and power low. Through-silicon vias (TSVs) and Through-glass vias (TGVs) are one of the core enablers – especially for 2.5D interposers and many 3D integration schemes.[i] But […]
Chipmetrics and Park Systems: Enabling the Next Generation of Semiconductor Metrology
As semiconductor devices continue to scale into fully three-dimensional architectures, traditional metrology approaches are reaching their limits. Advanced nodes, heterogeneous integration, and novel materials demand not only higher resolution – but deeper insight into how nanoscale physical properties translate into yield, reliability, and performance. Against this backdrop, Chipmetrics and Park Systems are working together to […]
Chipmetrics 2025: A Year of Momentum, Discovery, and Record Growth
As 2025 comes to a close, one thing is clear at Chipmetrics: this was a year of meaningful progress – scientifically, commercially, and organizationally. From record sales and major revenue milestones to new discoveries and geographic expansion, the past twelve months have laid strong foundations for an even more ambitious 2026. To capture the year […]
Metrology Alone Isn’t Enough for Next-Generation 3D NAND
A recent Semiconductor Engineering article, “Metrology Digs Deep to Produce Next-Generation 3D NAND,” highlights the growing difficulty of measuring and controlling increasingly complex 3D NAND structures as the industry pushes toward higher stack counts and ever more extreme aspect ratios. The message is clear: as 3D NAND architectures scale vertically, metrology must evolve just as […]
Pocket wafers + test chips for ALD: faster conformality learning, lower risk
Atomic layer deposition (ALD) lives or dies by conformality and surface chemistry. Pocket wafers loaded with discrete ALD test chips let you characterize both – quickly – on real 200/300 mm tools without burning product wafers. TL;DR A pocket wafer is a carrier wafer with machined/etched pockets that can hold separate test chips (coupons). For ALD, […]
PillarHall® LHAR5: Accelerating ALD Process Control in Next-Generation Memory Fabs
Executive Summary As semiconductor device geometries enter the 3D era, the complexity of Atomic Layer Deposition (ALD) processes for DRAM and other advanced memories has escalated. The PillarHall LHAR5 chip provides an in-situ, repeatable means to evaluate ALD conformality, film uniformity, and process drift under true production conditions. By integrating LHAR5 pocket wafers into existing […]
Spotting a “Second Growth Front” in ALD Trenches
Atomic Layer Deposition (ALD) is prized for coating deep, high-aspect-ratio (HAR) features. Using Chipmetrics’ PillarHall® lateral HAR test structures, we have now identified an unexpected second growth front that starts at the closed end of the trench and advances toward the entrance, meeting the primary front in the middle. How we saw it Imaging spectroscopic […]
Chipmetrics Strengthens Its Presence in Japan and East Asia to Support Advanced Semiconductor Development
To better serve one of its core markets, CEO Mikko Utriainen relocates to Japan’s capital. Tokyo, Japan – October 13, 2025 – Chipmetrics, a leading provider of advanced metrology solutions for the semiconductor industry, is strengthening its presence in Japan as part of its broader strategy to support customers across East Asia. To lead this […]
Chipmetrics Webinar: Computational Modelling of (AS-)ALD
Join us for an exclusive Chipmetrics webinar featuring Prof. Dr. Ralf Tonner-Zech from Leipzig University, who will share his expertise on computational modelling in (Area Selective) Atomic Layer Deposition. Topic: Computational Modelling of (AS-)ALD: From Fundamentals to Design StrategiesDate: 25 November 2025Time: 5:00 PM CETSpeaker: Prof. Dr. Ralf Tonner-Zech, Theoretical Chemistry of Complex Matter, Faculty […]
Unlocking Bottleneck Effects in 3D Semiconductor Structures with PillarHall Lateral High Aspect Ratio(LHAR) Test Chips
The Challenge: Conformality in Complex Geometries Atomic Layer Deposition (ALD) is the go-to technique for achieving ultra-thin, conformal films in the deep, narrow features found in advanced semiconductors, batteries, and capacitors. However, as device designs push into ever-more complex 3D geometries, a hidden challenge emerges: bottlenecks in High Aspect Ratio (HAR) structures can disrupt film […]
