Conformality was everywhere: Chipmetrics at ALD/ALE 2026
Tampa, Florida – June 29 to July 2, 2026 ALD/ALE 2026 is behind us. Chipmetrics contributed two presentations this year, an oral talk on high surface area micro-loading effect and a poster on platinum ALD with Aalto University. We also had the pleasure of seeing PillarHall user cases appear on other slides and posters. Here […]
Chipmetrics announces new ASD-2 test chip with customizable metal–dielectric material stacks
Chipmetrics is expanding its Area-Selective Deposition test chip portfolio with ASD-2, a new multi-material test chip platform designed to help semiconductor process teams evaluate selective deposition on advanced metal–dielectric surfaces. Building on the foundation of the ASD-1 test chip, ASD-2 introduces a more flexible approach to ASD process development: a variable material stack that can […]
Chipmetrics Introduces Pre-Patterned Electrical Test Structure for Rapid Thin-Film Characterization
Finnish metrology specialist launches a pre-patterned electrical test structure that enables electrical characterization immediately after film deposition. Joensuu, Finland — March 17, 2026 — Chipmetrics today announced a new pre-patterned electrical test structure designed to dramatically simplify electrical characterization of thin films used in semiconductor process development and advanced materials research. The structure enables immediate […]
TSV R&D: Everyone’s Problem in Advanced Packaging
Vertical connectivity is a key element of Advanced Packaging: The implementation of Silicon Interposers and chip stacking allows shorter and more dense electrical connections which reduce signal delay and power low. Through-silicon vias (TSVs) and Through-glass vias (TGVs) are one of the core enablers – especially for 2.5D interposers and many 3D integration schemes.[i] But […]
Chipmetrics and Park Systems: Enabling the Next Generation of Semiconductor Metrology
As semiconductor devices continue to scale into fully three-dimensional architectures, traditional metrology approaches are reaching their limits. Advanced nodes, heterogeneous integration, and novel materials demand not only higher resolution – but deeper insight into how nanoscale physical properties translate into yield, reliability, and performance. Against this backdrop, Chipmetrics and Park Systems are working together to […]
Chipmetrics 2025: A Year of Momentum, Discovery, and Record Growth
As 2025 comes to a close, one thing is clear at Chipmetrics: this was a year of meaningful progress – scientifically, commercially, and organizationally. From record sales and major revenue milestones to new discoveries and geographic expansion, the past twelve months have laid strong foundations for an even more ambitious 2026. To capture the year […]
Metrology Alone Isn’t Enough for Next-Generation 3D NAND
A recent Semiconductor Engineering article, “Metrology Digs Deep to Produce Next-Generation 3D NAND,” highlights the growing difficulty of measuring and controlling increasingly complex 3D NAND structures as the industry pushes toward higher stack counts and ever more extreme aspect ratios. The message is clear: as 3D NAND architectures scale vertically, metrology must evolve just as […]
Pocket wafers + test chips for ALD: faster conformality learning, lower risk
Atomic layer deposition (ALD) lives or dies by conformality and surface chemistry. Pocket wafers loaded with discrete ALD test chips let you characterize both – quickly – on real 200/300 mm tools without burning product wafers. TL;DR A pocket wafer is a carrier wafer with machined/etched pockets that can hold separate test chips (coupons). For ALD, […]
PillarHall® LHAR5: Accelerating ALD Process Control in Next-Generation Memory Fabs
Executive Summary As semiconductor device geometries enter the 3D era, the complexity of Atomic Layer Deposition (ALD) processes for DRAM and other advanced memories has escalated. The PillarHall LHAR5 chip provides an in-situ, repeatable means to evaluate ALD conformality, film uniformity, and process drift under true production conditions. By integrating LHAR5 pocket wafers into existing […]
Spotting a “Second Growth Front” in ALD Trenches
Atomic Layer Deposition (ALD) is prized for coating deep, high-aspect-ratio (HAR) features. Using Chipmetrics’ PillarHall® lateral HAR test structures, we have now identified an unexpected second growth front that starts at the closed end of the trench and advances toward the entrance, meeting the primary front in the middle. How we saw it Imaging spectroscopic […]
