Spatial Atomic Layer Deposition (ALD): Unveiling New Frontiers in Material Processing with Mike van de Poll
Mike van de Poll, a researcher at Eindhoven University of Technology, has dedicated his scientific endeavors to exploring the intricacies of spatial Atomic Layer Deposition (ALD). Supervised by renowned experts in the field, Erwin Kessels and Bart Macco, Mike’s research dives deep into understanding fundamental aspects of spatial ALD, leveraging the advanced capabilities of Chipmetrics’ […]
Our Picks Ahead of ALD/ALE 2025
Anticipating Atomic Layer Innovation in South Korea As the semiconductor industry surges toward ever-more complex device architectures, ALD 2025 stands out as a premier venue for discovering the innovations that will define next-generation atomic-scale processing. From addressing high aspect ratio (HAR) challenges to developing new materials and precision etching techniques, the conference program is packed […]
Enabling Next-Generation Silicon Capacitors with ALD and PillarHall
As electronic systems continue to scale in speed, complexity, and miniaturization, the demands placed on power delivery and signal integrity have never been greater. Silicon capacitors, key components for decoupling and noise suppression in high-performance circuits, must now meet extreme requirements for low impedance, high capacitance density, and minimal parasitics – all within shrinking footprints. […]
Chipmetrics Welcomes Stefan Polzin as New Chief Operating Officer
Chipmetrics is delighted to announce the appointment of Stefan Polzin as our new Chief Operating Officer, bringing a wealth of experience and enthusiasm to our growing team. Originally from Weißwasser and now residing in Dresden, Germany, Stefan holds a Master’s in Electrical Engineering and an Executive MBA in General Management from IESE Business School. With […]
Chipmetrics to Host Exclusive 3D Thin Film Metrology Workshop in Jeju – June 26, 2025
Chipmetrics announces its upcoming 3D Thin Film Metrology Workshop, taking place on June 26, 2025, at the Parnas Hotel in Jeju Island, South Korea, immediately following the ALD/ALE 2025 Conference. This one-day, in-person event offers a rare opportunity for experts and newcomers alike to come together and discuss the latest developments, challenges, and innovations in […]
Challenges of Transferring Deposition Processes to Industry Partners in the Semiconductor Industry
The ongoing struggle to uphold Moore’s law leads to increasing scaling demands for semiconductor device structures. In order to facilitate these needs the introduction of 3D structures has been accelerated by the industry. This is especially evident in 3D NAND memory structures, Though Silicon Vias (TSVs) and new transistor architectures like nanosheet designs. All of […]
Streamline Semiconductor Tool Qualification with PillarHall Test Chips
Staying competitive hinges on getting new tools up and running as quickly and efficiently as possible, be it brand new tools or after maintenance. Yet, the qualification process for deposition equipment can be a major bottleneck – one that often involves lengthy cycles, costly materials, and complex data analysis. Our PillarHall series of test chips […]
